Flash memory devices, which are nonvolatile memory devices, can maintain data in memory cells even if electric power is removed from the device. Additionally, flash memory devices may be electrically erased at high speeds on a circuit board.
The technologies for the flash memory devices have continuously advanced by developing various cell structures such as stacked gate cells, split gate cells, source side injection cells and etc. U.S Pat. No. 5,455,792 describes such various cell structures.
The stacked gate cell configuration includes a floating gate and a control gate formed on the floating gate. U.S. Pat. No. 4,698,787 describes one embodiment of the stacked gate cell. Referring to FIG. 1, a floating gate 11 is formed on a substrate 10. A control gate 12 is formed on the floating gate 11. An ONO (Oxide-Nitride-Oxide) layer (not shown) may be formed between the control gate 12 and the floating gate 11. Program operations are performed in a drain region 14 through a CHEI (Channel Hot Electron Injection). Erase operations are performed in a source region 13 though F-N (Fowler-Nordheim) tunneling. Because the size of a resulting cell is relatively small, the stacked gate cell has been prevalently used as the unit cell of flash memory devices.
On the other hand, U.S. Pat. No. 5,358,885 discloses a method for fabricating a T-shaped gate electrode (i.e., the upper part of the gate electrode is larger than the lower part of the gate electrode) for reduced resistance between the T-shaped gate electrode and a source region. Korean Patent Publication No.2003-51038 discloses a method for fabricating a T-shaped gate electrode by forming damascene structures and, particularly, a method for preventing the deterioration of a metallic salicide layer in a later thermal process and reducing the resistance of the T-shaped gate electrode by enlarging the area for the metallic salicide layer on the gate electrode.
According to conventional methods, dopants in source and drain extension regions are diffused toward a channel region by a later thermal treatment. Thus, if the width of a gate electrode is less than 0.06 micrometers (μm), the source region will be connected to the drain region. Thus, a metal oxide semiconductor (MOS) transistor is virtually impossible to achieve. Moreover, even if the width of the gate electrode is more in width than 0.06 μm, the depth of the source and drain junctions have to be less than 10 μm, therefore causing serious short channel effects. In addition, as the design size of a transistor decreases, the depth of the source and drain junctions has to be proportionally shallow, thereby causing several problems such as parasitic resistances and junction leakages due to the silicide layer later formed on the shallow source and drain regions.
Accordingly, various elevated source and drain structures have been suggested to solve such problems in conventional arts. However, the elevated source and drain structures require additional selective epitaxial processes, thereby increasing manufacturing cost, and presenting difficulties in the implementation of a manufacturing process.